Electrical interconnection and thin film transistor fabrication mehods, and integrated circuitry

ABSTRACT

An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

TECHNICAL FIELD

[0001] This invention relates to electrical interconnection and thinfilm transistor fabrication methods, and to integrated circuitry havingelectrically interconnected layers.

BACKGROUND OF THE INVENTION

[0002] The invention grew out of needs associated with thin filmtransistors (TFTs) and their usage in high-density static random accessmemories (SRAMs). A static memory cell is characterized by operation inone of two mutually exclusive and cell-maintaining operating states.Each operating state defines one of the two possible binary bit values,zero or one. A static memory cell typically has an output which reflectsthe operating state of the memory cell. Such an output produces a “high”voltage to indicate a “set” operating state. The memory cell outputproduces a “low” voltage to indicate a “reset” memory cell operatingstate. A low or reset output voltage usually represents a binary valueof zero, and a high or set output voltage represents a binary value ofone.

[0003] A static memory cell is said to be bi-stable because it has twostable or self-maintaining operating states, corresponding to twodifferent output voltages. Without external stimuli, a static memorycell will operate continuously in a single one of its two operatingstates. It has internal feedback to maintain a stable output voltage,corresponding to the operating state of the memory cell, as long as thememory cell receives power.

[0004] The operation of a static memory cell is in contrast to othertypes of memory cells, such as dynamic cells, which do not have stableoperating states. A dynamic memory cell can be programmed to store avoltage which represents one of two binary values, but requires periodicreprogramming or “refreshing” to maintain this voltage for more thanvery short time periods. A dynamic memory cell has no feedback tomaintain a stable output voltage. Without refreshing, the output of adynamic memory cell will drift toward intermediate or indeterminatevoltages, effectively resulting in loss of data.

[0005] Dynamic memory cells are used in spite of this limitation becauseof the significantly greater packaging densities which can be attained.For instance, a dynamic memory cell can be fabricated with a singleMOSFET transistor, rather than the six transistors typically required ina static memory cell. Because of the significantly differentarchitectural arrangements and functional requirements of static anddynamic memory cells and circuits, static memory design has developedalong a different path than has the design of dynamic memories.

[0006] Ongoing efforts in SRAM circuitry to improve active loads hasbrought about the development of TFTs in attempts to provide low leakagecurrent as well as high noise immunity. While the invention grew out ofneeds associated with TFTs of SRAM circuitry, the artisan willappreciate applicability of the invention to other types of circuitry.

[0007] Some recent TFT technology employs fully surrounded field effecttransistor (PET) gate regions, such as shown in FIG. 1. Such illustratesa semiconductor wafer fragment 10 comprised of a bulk substrate 12 andoverlying insulating layer 14. Bulk substrate 12 includes an n+ activearea 16 which electrically connects with a gate of a thin filmtransistor, which is generally indicated by numeral 18. Such transistorincludes a channel region 20. The adjacent source and drain of suchtransistor would be into and out of the plane of the paper on which FIG.1 appears. A first or bottom gate conductive layer 22 is provided overinsulating layer 14 and extends to electrically connect with active area16. A bottom gate oxide dielectric layer 24 is provided atop bottom gatelayer 22 and contacts with the bottom of transistor channel region 20. Atop gate layer 26 overlies bottom dielectric layer 24 and the top oftransistor channel region 20. An electrically conductive top is gatelayer 28 is provided and patterned over top gate oxide dielectric layer26. A contact opening 30 is provided through top and bottom gate oxidelayers 26, 24 respectively, over active area 16 prior to top gate layer28 deposition. Such results in electrical interconnection of top gate 28with a bottom gate 22. Thus, channel region 20 is surrounded byconductive gate material for switching transistor 18 “on”.

[0008] The above described construction requires photolithography andetch steps for producing contact opening 30, and separate patterning oftop gate electrode 23. It would be desirable to provide methods offorming thin film transistors which minimize photolithography andetching steps.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0010]FIG. 1 is a diagrammatic section of a semiconductor wafer fragmentprocessed in accordance with prior art methods, and is described in the“Background” section above.

[0011]FIG. 2 is a diagrammatic section of a semiconductor wafer fragmentprocessed in accordance with the invention. Such view is a section ofthe wafer fragment taken along a position relative to line Y-Y in FIG.4.

[0012]FIG. 3 is a view of the FIG. 2 wafer fragment taken at a sameprocessing step as that illustrated by FIG. 2. Such view is a section ofthe wafer fragment taken along a position relative to line X-X in FIG.4.

[0013]FIG. 4 is a diagrammatic top plan view of the FIG. 2 waferfragment taken at the same processing step as that illustrated by FIG.2.

[0014]FIG. 5 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 2.

[0015]FIG. 6 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 3 and corresponding in process sequence to that ofFIG. 5.

[0016]FIG. 7 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 5.

[0017]FIG. 8 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 6 and corresponding in process sequence to that ofFIG. 7.

[0018]FIG. 9 is a top plan view of the FIG. 2 wafer fragment taken atthe same processing step as that illustrated by FIG. 7.

[0019]FIG. 10 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 7.

[0020]FIG. 11 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 8 and corresponding in process sequence to that ofFIG. 10.

[0021]FIG. 12 is a top plan view of the FIG. 2 wafer fragment taken atthe same processing step as that illustrated by FIG. 10.

[0022]FIG. 13 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 10.

[0023]FIG. 14 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 10 and corresponding in process sequence to that ofFIG. 13.

[0024]FIG. 15 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 13.

[0025]FIG. 16 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 14 and corresponding in process sequence to that ofFIG. 15.

[0026]FIG. 17 is a top plan view of the FIG. 2 wafer fragment taken atthe same processing step as that illustrated by FIG. 15.

[0027]FIG. 18 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 15.

[0028]FIG. 19 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 3, but at a process step subsequent to thatillustrated by FIG. 16 and corresponding ill process sequence to that ofFIG. 18.

[0029]FIG. 20 is a top plan view of the FIG. 2 wafer fragment taken atthe same processing step as that illustrated by FIG. 18.

[0030]FIG. 21 is a view of the FIG. 2 wafer fragment taken at the samerelative position as FIG. 2, but at a process step subsequent to thatillustrated by FIG. 18.

[0031]FIG. 22 is a top plan view of the FIG. 2 wafer fragment taken atthe same processing step as that illustrated by FIG. 21.

[0032]FIG. 23 is a diagrammatic section of an alternate wafer fragmentat a processing step in accordance with another aspect of the invention.

[0033]FIG. 24 is a view of the FIG. 23 wafer fragment taken at aprocessing step subsequent to that illustrated by FIG. 23.

[0034]FIG. 25 is a view of the FIG. 23 wafer fragment taken at aprocessing step subsequent to that illustrated by FIG. 24.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0036] In the context of this document, “electrically conductivematerial” signifies a material which is inherently conductive asdeposited, or capable of being rendered electrically conducted bysubsequent processing steps or applications of conventional operationalelectric fields.

[0037] In accordance with one aspect of the invention, a method offabricating a bottom and top gated thin film transistor comprises thefollowing steps:

[0038] providing an electrically conductive bottom thin film transistorgate electrode layer on a semiconductor substrate, the bottom gateelectrode layer having a planarized outer surface, the outer surfacehaving a surface area;

[0039] providing a bottom gate dielectric layer over the bottom gateelectrode layer;

[0040] providing a thin film transistor body layer over the bottom gatelayer;

[0041] defining source, drain and channel regions within the thin filmbody layer;

[0042] providing a top gate dielectric layer over the thin filmtransistor body layer;

[0043] providing an electrically conductive top transistor gateelectrode layer over the top gate dielectric layer;

[0044] etching the composite top gate electrode, top gate dielectric,and body layers in a pattern which defines a top gate electrode, topgate dielectric and body outline which is received only partially withinthe bottom gate electrode outer surface area, the bottom gate electrodeouter surface area including a portion extending outwardly beyond theoutline, the etching defining outwardly exposed top gate electrode andbody sidewalls;

[0045] providing a layer of insulating dielectric over the etched topgate electrode and outwardly exposed sidewalls;

[0046] anisotropically etching the insulating dielectric layer to definean insulating sidewall spacer, the sidewall spacer leaving the top gateelectrode sidewall outwardly exposed;

[0047] outwardly exposing bottom gate electrode surface area extendingoutwardly beyond the outline;

[0048] providing a layer of electrically conductive material over theoutwardly exposed top gate electrode sidewall and outwardly exposedbottom gate electrode surface area; and

[0049] anisotropically etching the layer of conducting material todefine an electrically conductive sidewall link electricallyinterconnecting the top gate electrode sidewall and bottom gateelectrode outer surface.

[0050] In accordance with another aspect of the invention, an electricalinterconnection method comprises:

[0051] providing two conductive layers separated by an insulatingmaterial on a semiconductor wafer;

[0052] etching the conductive layers and insulating material to defineand outwardly expose a sidewall of each conductive layer;

[0053] depositing an electrically conductive material over the etchedconductive layers and their respective sidewalls; and

[0054] anisotropically etching the conductive material to define anelectrically conductive sidewall link electrically interconnecting thetwo conductive layers.

[0055] In accordance with still a further aspect of the invention, anelectrical interconnection method comprises:

[0056] providing inner and outer conductive layers separated by aninsulating material on a semiconductor wafer;

[0057] etching the conductive layers and insulating material to defineand outwardly expose a sidewall of the outer conductive layer and tooutwardly expose the inner conductive layer;

[0058] depositing an electrically conductive material over the etchedconductive layers, the electrically conductive material contacting theouter conductive layer exposed sidewall and exposed inner conductivelayer; and

[0059] anisotropically etching the conductive material to define anelectrically conductive sidewall link electrically interconnecting thetwo conductive layers.

[0060] The invention also contemplates integrated circuitry formed inaccordance with the above methods, and well as other integratedcircuitry.

[0061] More specifically and referring initially to FIGS. 2-4, asemiconductor wafer fragment is indicated generally by reference numeral32. Such comprises a gate oxide layer 34 and word line 36. Bulksubstrate would exist below gate oxide 34, and is not shown for clarity.Word line 36 is comprised of insulating regions 38, electricallyconductive polysilicon region 40, and overlying electrically conductivesilicide region 42. An insulating oxide layer 44 and subsequentinsulative nitride layer 46 are provided over word line 36. Layers 46and 44 have been photo-patterned and etched to produce a bottomelectrode contact outline 48 (FIG. 4) which extends inwardly to exposeand ultimately provide electrical connection silicide region 42 of wordline 36. The etch is timed such that silicide region 42 is reached withminimal over-etch such that the adjacent substrate is not reached.Subsequently, a layer of electrically conductive material, preferablypolysilicon, is deposited atop the wafer to a thickness sufficient tocompletely fill bottom thin film transistor gate electrode outline 48.Such layer is then chemical-mechanical polished (CMP) to isolate anddefine an electrically conductive bottom thin film transistor gateelectrode 50 on a semiconductor substrate. Such electrode has aplanarized outer surface 52 and an outer surface area defined by outline48. A more detailed description of forming such a construction iddescribed in our co-pending U.S. patent application Ser. No. 08/061,402,filed on May 12, 1993, and entitled “Fully Planarized Thin FilmTransistor (TFT) and Process To Fabricate Same”, which is herebyincorporated by reference.

[0062] Referring to FIGS. 5 and 6, a bottom gate dielectric layer 54 isprovided over bottom gate electrode layer 50. Such preferably comprisesSiO₂ deposited to a thickness of from about 100 Angstroms to about 500Angstroms. A thin film transistor body layer 56 is provided over bottomgate layer 54. Such is preferably amorphous silicon as-deposited, whichis then transformed to polycrystalline silicon by solid phasecrystallization technique. Such preferably is provided to a thickness offrom about 100 Angstroms to about 700 Angstroms. A conventional V_(t) n−adjust implant into layer 56 would then preferably be provided. A topgate dielectric layer 58 is provided over thin film transistor bodylayer 56. Such preferably comprises SiO₂ deposited to a thickness offrom about 100 Angstroms to about 500 Angstroms. An electricallyconductive top transistor gate electrode layer 60 is provided over topgate dielectric layer 58. Such preferably comprises in situ conductivelydoped polysilicon deposited to a thickness of about 2,000 Angstroms.Thus, and for purposes of the continuing discussion, inner and outerconductive layers 50 and 60 respectively, are provided on asemiconductor wafer. Such are separated by an insulating material in theform of dielectric layers 54 and 58, and the insulative nature ofsemiconductor material 56.

[0063] Referring to FIGS. 7-9, composite top gate electrode, top gatedielectric, and body layers 60, 58, and 56 respectively, are etched in apattern which defines an electrically conductive top gate electrode 62,top gate dielectric and body outline 64 which is received only partiallywithin bottom gate electrode outer surface area 48. Preferably and as isshown, such composite etching is preferably conducted to be selective tobottom gate dielectric layer 54. Bottom gate electrode outer surfacearea 48 (FIG. 9) includes portions 66 which extend outwardly beyondoutline 64. For purposes of the continuing discussion, such compositeetching defines an opposing pair of outwardly exposed top gate electrodesidewalls 68, 70, and an opposing pair of body sidewalls 72 and 74.

[0064] Referring to FIGS. 10-12, a layer of insulating dielectric, suchas SiO₂, is provided over etched top gate electrode 62 and outwardlyexposed sidewalls 68, 70, 72 and 74. Such layer is anisotropicallyetched to define insulating sidewall spacers 76 and 78 which leaves topgate electrode 62 outer sidewalls 68 and 70 outwardly exposed. Mostpreferably, such anisotropic etching is conducted without anyphotomasking relative to spacers 76 and 78 formation, to outwardlyexpose approximately 800 Angstroms of sidewalls 76 and 78 elevation.Photomasking might occur elsewhere with respect to the wafer, butpreferably not for the purposes of forming such sidewall spacers. Mostpreferably, no photomasking occurs during this etching step. As shown,such insulating layer is preferably etched to form spacers 76 and 78which partially overlap outwardly exposed top gate electrode sidewalls68 and 70. yet provide outwardly exposed portions as well. Such etchingis also conducted to etch bottom gate dielectric layer 54 to outwardlyexpose bottom gate electrode upper surface area portions 66 which extendoutwardly beyond outline 64. Thus, bottom gate electrode is surface area66 extending outwardly beyond outline 64 is outwardly exposed. Further,inner and outer conductive layers 50 and 52 respectively are thus etchedto outwardly expose a sidewall of outer conductive layer 60, and tooutwardly expose inner conductive layer 50. Alternately considered, thinfilm transistor body layer 56 can be considered as a mid-conductivelayer, or more accurately a conductive capable layer, which iselectrically isolated from and positioned between inner and outerconductive layers 60 and 50, respectively. Mid-conductive layer 56 thusincludes sidewalls 72 and 74 which are covered by an insulating materialin the form of spacers 76 and 78. The preferred thickness of the layerfrom which spacers 76 and 78 are formed is about 150 to400 Angstroms,leaving the width of spacers 76 and 78 at preferably about 100 to 350Angstroms.

[0065] Referring to FIGS. 13 and 14, a layer 80 of electricallyconductive material is provided over the outwardly exposed top gateelectrode 62 sidewalls 68 and 70, and over insulating spacers 76 and 78,and over outwardly exposed bottom gate electrode surface area portions66. Layer 80 preferably comprises in situ conductively doped polysiliconprovided to a thickness of about 1,000 Angstroms. As will be appreciatedby the artisan, electrical interconnection has thus been made betweentop gate electrode 62 and bottom gate electrode 50 without the typicaladded associated photo lithography step for connecting such electrodesas is shown by FIG. 1.

[0066] Referring to FIGS. 15-17, layer 80 is anisotropically etched todefine electrically conductive sidewall links 82 and 84 whichelectrically interconnect top gate electrode sidewalls 68, 70, andbottom gate electrode surface area portions 66. Such anisotropic etchingis again preferably conducted without any photomasking relative to thesidewall link formation, while photomasking might occur elsewhere on thewafer. Most preferably, no photomasking occurs during this etching step.

[0067] Referring to FIGS. 18-20, a layer of photoresist 86 is depositedand patterned, and top electrode layer 60 subsequently etched to providethe illustrated offset of top gate electrode 62 relative to bottom gateelectrode 50. Preferably, the etch of polysilicon 60 is terminated in anisotropic undercut etch to optionally enable a p− LDD implant into aregion between p+ source/drain regions and transistor body region 56.

[0068] Referring to FIGS. 21 and 22, the masked wafer is subjected to ap+ implant (with resist layer 86 still in place) for definition ofsource and drain regions 92, 88 respectively. Such also effectivelydefines a channel region 90 within thin film transistor body layer 56.Channel region overlaps with the bottom gate electrode, and has aninsulated sidewall (FIG. 19). Thus in accordance with the abovedescribed method, source/drain and channel regions are effectivelydefined by anisotropic etching of the layer of conductive materialutilized to form sidewall interconnecting links 82 and 84. Preferably,top gate electrode 62 underlaps bottom gate electrode 50 on the sourceand overlaps bottom gate electrode 50 on the drain side, as is shown. Ifdesired, the illustrated resist overhang can be utilized for providing ablanket p− implant 89 after the p+ implant is done with resist still inplace, and then the resist is stripped off (to provide a PMOS LDDstructure).

[0069] Further aspects of the invention are described with reference toFIGS. 23-25. Such illustrates a semiconductor wafer fragment 94 of abulk substrate 95 and overlying insulating region 96. Two conductivelayers 97 and 98, separated by an insulating material layer 99, areprovided atop insulating layer 96. Such conductive and insulatingmaterials are etched, as shown, to define an opposing pair of outwardlyexposed sidewalls 100 a, 100 b, and 100 c, 100 d, for each conductivelayer.

[0070] Referring to FIG. 24, a layer 101 of an electrically conductivematerial is deposited over etched conductive layers 97 and 98 and theirrespective sidewalls 100 a, 100 b and 100 c, 100 d. The preferredmaterial for conductive layer 101 is in situ conductively dopedpolysilicon.

[0071] Referring to FIG. 25, layer 101 is subjected to an anisotropicetch to define a pair of electrically conductive sidewall links 103 and105 which effectively electrically interconnect conductive layers 97 and98. Such anisotropic etching is most preferably conducting without isphotomasking relative to the sidewall link formation, while other areasof the wafer might be masked. Most preferably, no photomasking occursduring this etching step.

[0072] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of fabricating a bottom and top gated thin film transistor comprising the following steps: providing an electrically conductive bottom thin film transistor gate electrode layer on a semiconductor substrate, the bottom gate electrode layer having a planarized outer surface, the outer surface having a surface area; providing a bottom gate dielectric layer over the bottom gate electrode layer; providing a thin film transistor body layer over the bottom gate layer; defining source, drain and channel regions within the thin film body layer; providing a top gate dielectric layer over the thin film transistor body layer; providing an electrically conductive top transistor gate electrode layer over the top gate dielectric layer; etching the composite top gate electrode, top gate dielectric, and body layers in a pattern which defines a top gate electrode, top gate dielectric and body outline which is received only partially within the bottom gate electrode outer surface area, the bottom gate electrode outer surface area including a portion extending outwardly beyond the outline, the etching defining outwardly exposed top gate electrode and body sidewalls; providing a layer of insulating dielectric over the etched top gate electrode and outwardly exposed sidewalls; anisotropically etching the insulating dielectric layer to define an insulating sidewall spacer, the sidewall spacer leaving the top gate electrode sidewall outwardly exposed; outwardly exposing bottom gate electrode surface area extending outwardly beyond the outline; providing a layer of electrically conductive material over the outwardly exposed top gate electrode sidewall and outwardly exposed bottom gate electrode surface area; and anisotropically etching the layer of conducting material to define an electrically conductive sidewall link electrically interconnecting the top gate electrode sidewall and bottom gate electrode outer surface.
 2. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein both anisotropic etches are conducted without photomasking relative to the spacer and sidewall link formations.
 3. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein the electrically conductive material and resultant sidewall link comprise polysilicon.
 4. The method of fabricating a bottom and top gated thin film transistor of claim 1 comprising forming the sidewall spacer to partially overlap the outwardly exposed top gate electrode sidewall.
 5. The method of fabricating a bottom and top gated thin film transistor of claim 1 comprising forming the sidewall spacer to partially overlap the outwardly exposed top gate electrode sidewall, and wherein the electrically conductive material and resultant sidewall link comprise polysilicon.
 6. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein both anisotropic etches are conducted without photomasking relative to the spacer and sidewall link formation, the sidewall spacer is formed to partially overlap the outwardly exposed top gate electrode sidewall, and the electrically conductive material and resultant sidewall link comprise polysilicon.
 7. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein the step of composite etching is conducted to be selective to the bottom gate dielectric layer, the step of anisotropically etching the insulating dielectric layer including etching of the bottom gate dielectric layer to outwardly expose bottom gate electrode surface area extending outwardly beyond the outline.
 8. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein the defining of the source and drain regions occurs after the anisotropic etching of the layer of conducting material.
 9. The method of fabricating a bottom and top gated thin film transistor of claim 1 wherein the step of composite etching defines an opposing pair of outwardly exposed top gate electrode sidewalls and an opposing pair of body sidewalls, the method further comprising formation of two sidewall spacers and two conductive sidewall links by the respective anisotropic etching steps.
 10. An electrical interconnection method comprising: providing two conductive layers separated by an insulating material on a semiconductor wafer; etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer, depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers.
 11. The electrical interconnection method of claim 10 wherein the anisotropic etch is conducted without photomasking relative to the sidewall link formation.
 12. The electrical interconnection method of claim 10 wherein the electrically conductive material and resultant sidewall link comprise polysilicon.
 13. The electrical interconnection method of claim 10 wherein the anisotropic etch is conducted without photomasking relative to the sidewall link formation, and the electrically conductive material and resultant sidewall link comprise polysilicon.
 14. The electrical interconnection method of claim 10 wherein the step of etching the conductive layers and insulating material defines an opposing pair of outwardly exposed sidewalls for each conductive layer, the method further comprising formation of two conductive sidewall links by such anisotropic etching.
 15. An electrical interconnection method comprising: providing inner and outer conductive layers separated by an insulating material on a semiconductor wafer; etching the conductive layers and insulating material to define and outwardly expose a sidewall of the outer conductive layer and to outwardly expose the inner conductive layer; depositing an electrically conductive material over the etched conductive layers, the electrically conductive material contacting the outer conductive layer exposed sidewall and exposed inner conductive layer; and anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers.
 16. The electrical interconnection method of claim 15 wherein the anisotropic etch is conducted. without photomasking relative to the sidewall link formation.
 17. The electrical interconnection method of claim 15 further comprising: prior to depositing and anisotropic etching of the electrically conductive material, providing a layer of insulating dielectric material over the etched conductive layers and insulating material; anisotropically etching the insulating dielectric layer to define an insulating sidewall spacer, the sidewall spacer leaving the outer conductive layer sidewall and inner conductive layer outwardly exposed; and the electrically conductive material being deposited over the sidewall spacer.
 18. The electrical interconnection method of claim 17 wherein both anisotropic etches are conducted without photomasking relative to the spacer and sidewall link formations.
 19. The electrical interconnection method of claim 17 comprising forming the sidewall spacer to partially overlap the outwardly exposed outer conductive layer sidewall.
 20. The electrical interconnection method of claim 15 wherein the electrically conductive material and resultant sidewall link comprise polysilicon.
 21. The electrical interconnection method of claim 15 wherein the step of etching the conductive layers and insulating material defines an opposing pair of outwardly exposed sidewalls for the top conductive layer, the method further comprising formation of two conductive sidewall links by such anisotropic etching.
 22. A bottom and top gated thin film transistor comprising: a conductive bottom thin film transistor gate electrode, the bottom gate electrode having a planarized outer surface, the outer surface having a surface area; a bottom gate dielectric layer atop the bottom gate electrode; a thin film transistor body layer over the bottom gate layer, the thin film transistor body layer having source, drain and channel regions, the channel region overlapping with the bottom gate electrode, the channel region having an insulated sidewall; a top gate dielectric layer over the thin film transistor body layer; an electrically conductive top thin film transistor gate electrode over the top gate dielectric layer, the top gate electrode overlapping with the channel region, the top gate electrode having an electrically conductive sidewall, the bottom gate electrode outer surface area is including a portion extending outwardly beyond the top gate electrode sidewall; and an electrically conductive sidewall link overlying the electrically insulated channel region sidewall and extending between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes.
 23. The bottom and top gated thin film transistor of claim 22 wherein the electrically conductive sidewall link comprises polysilicon.
 24. The bottom and top gated thin film transistor of claim 22 wherein the insulated channel region sidewall is insulated by an insulating sidewall spacer, the insulating sidewall spacer partially overlapping the top gate electrode electrically conductive sidewall.
 25. The bottom and top gated thin film transistor of claim 22 wherein the electrically conductive sidewall link comprises polysilicon, and the insulated channel region sidewall is insulated by an insulating sidewall spacer, the insulating sidewall spacer partially overlapping the top gate electrode electrically conductive sidewall.
 26. The bottom and top gated thin film transistor of claim 22 further comprising the channel region having an opposing pair of insulated sidewalls and the top gate electrode having an opposing pair of electrically conductive sidewalls, the transistor further comprising two conductive sidewall links.
 27. An integrated circuit comprising: two conductive layers separated by an insulating material on a semiconductor wafer, the conductive layers each having an outer sidewall; and an electrically conductive sidewall link positioned over and electrically interconnecting the respective outer sidewalls of the two conductive layers.
 28. The integrated circuit of claim 27 wherein the sidewall link comprises polysilicon.
 29. The integrated circuit of claim 27 wherein the conductive layers each comprise a respective pair of opposed outer sidewalls, the integrated circuit further comprising two conductive sidewall links.
 30. The integrated circuit of claim 27 wherein the conductive layers each comprise a respective pair of opposed outer sidewalls, the integrated circuit further comprising two conductive sidewall links, the two conductive sidewall links comprising polysilicon.
 31. An integrated circuit comprising: inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface; and an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface.
 32. The integrated circuit of claim 31 wherein the sidewall link comprises polysilicon.
 33. The integrated circuit of claim 31 wherein the conductive layers each comprise a respective pair of opposed outer sidewalls, the integrated circuit further comprising two conductive sidewall links.
 34. The integrated circuit of claim 31 wherein the conductive layers each comprise a respective pair of opposed outer sidewall, the integrated circuit further comprising two conductive sidewall links, the sidewall links comprising polysilicon.
 35. The integrated circuit of claim 31 further comprising a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the electrically conductive sidewall link being positioned over the insulting material.
 36. The integrated circuit of claim 31 further comprising a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link being positioned over the insulting material.
 37. The integrated circuit of claim 31 further comprising a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the electrically conductive sidewall link comprising polysilicon and being positioned over the insulting material.
 38. The integrated circuit of claim 31 .further comprising a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link comprising polysilicon and being positioned over the insulting material.
 39. A thin film transistor produced according to the method of claim
 1. 40. Integrated circuitry produced according to the method of claim
 10. 41. Integrated circuitry produced according to the method of claim
 15. 